/**
 * \file IfxRif_bf.h
 * \brief
 * \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
 *
 *
 * Date: 2015-12-17 16:14:46 GMT
 * Version: TBD
 * Specification: TBD
 * MAY BE CHANGED BY USER [yes/no]: No
 *
 *                                 IMPORTANT NOTICE
 *
 *
 * Infineon Technologies AG (Infineon) is supplying this file for use
 * exclusively with Infineon's microcontroller products. This file can be freely
 * distributed within development tools that are supporting such microcontroller
 * products.
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
 * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
 * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
 *
 * \defgroup IfxLld_Rif_Registers_BitfieldsMask Bitfields mask and offset
 * \ingroup IfxLld_Rif_Registers
 * 
 */
#ifndef IFXRIF_BF_H
#define IFXRIF_BF_H 1
/******************************************************************************/
/******************************************************************************/
/** \addtogroup IfxLld_Rif_BitfieldsMask
 * \{  */
/** \brief Length for Ifx_RIF_CLC_Bits.DISR */
#define IFX_RIF_CLC_DISR_LEN (1u)

/** \brief Mask for Ifx_RIF_CLC_Bits.DISR */
#define IFX_RIF_CLC_DISR_MSK (0x1u)

/** \brief Offset for Ifx_RIF_CLC_Bits.DISR */
#define IFX_RIF_CLC_DISR_OFF (0u)

/** \brief Length for Ifx_RIF_CLC_Bits.DISS */
#define IFX_RIF_CLC_DISS_LEN (1u)

/** \brief Mask for Ifx_RIF_CLC_Bits.DISS */
#define IFX_RIF_CLC_DISS_MSK (0x1u)

/** \brief Offset for Ifx_RIF_CLC_Bits.DISS */
#define IFX_RIF_CLC_DISS_OFF (1u)

/** \brief Length for Ifx_RIF_CLC_Bits.EDIS */
#define IFX_RIF_CLC_EDIS_LEN (1u)

/** \brief Mask for Ifx_RIF_CLC_Bits.EDIS */
#define IFX_RIF_CLC_EDIS_MSK (0x1u)

/** \brief Offset for Ifx_RIF_CLC_Bits.EDIS */
#define IFX_RIF_CLC_EDIS_OFF (3u)

/** \brief Length for Ifx_RIF_ID_Bits.MODREV */
#define IFX_RIF_ID_MODREV_LEN (8u)

/** \brief Mask for Ifx_RIF_ID_Bits.MODREV */
#define IFX_RIF_ID_MODREV_MSK (0x0u)

/** \brief Offset for Ifx_RIF_ID_Bits.MODREV */
#define IFX_RIF_ID_MODREV_OFF (0u)

/** \brief Length for Ifx_RIF_ID_Bits.MODTYPE */
#define IFX_RIF_ID_MODTYPE_LEN (8u)

/** \brief Mask for Ifx_RIF_ID_Bits.MODTYPE */
#define IFX_RIF_ID_MODTYPE_MSK (0xffu)

/** \brief Offset for Ifx_RIF_ID_Bits.MODTYPE */
#define IFX_RIF_ID_MODTYPE_OFF (8u)

/** \brief Length for Ifx_RIF_ID_Bits.MODNUMBER */
#define IFX_RIF_ID_MODNUMBER_LEN (16u)

/** \brief Mask for Ifx_RIF_ID_Bits.MODNUMBER */
#define IFX_RIF_ID_MODNUMBER_MSK (0xffffu)

/** \brief Offset for Ifx_RIF_ID_Bits.MODNUMBER */
#define IFX_RIF_ID_MODNUMBER_OFF (16u)

/** \brief Length for Ifx_RIF_ESI_Bits.CP */
#define IFX_RIF_ESI_CP_LEN (1u)

/** \brief Mask for Ifx_RIF_ESI_Bits.CP */
#define IFX_RIF_ESI_CP_MSK (0x1u)

/** \brief Offset for Ifx_RIF_ESI_Bits.CP */
#define IFX_RIF_ESI_CP_OFF (0u)

/** \brief Length for Ifx_RIF_ESI_Bits.FP */
#define IFX_RIF_ESI_FP_LEN (1u)

/** \brief Mask for Ifx_RIF_ESI_Bits.FP */
#define IFX_RIF_ESI_FP_MSK (0x1u)

/** \brief Offset for Ifx_RIF_ESI_Bits.FP */
#define IFX_RIF_ESI_FP_OFF (1u)

/** \brief Length for Ifx_RIF_ESI_Bits.DP0 */
#define IFX_RIF_ESI_DP0_LEN (1u)

/** \brief Mask for Ifx_RIF_ESI_Bits.DP0 */
#define IFX_RIF_ESI_DP0_MSK (0x1u)

/** \brief Offset for Ifx_RIF_ESI_Bits.DP0 */
#define IFX_RIF_ESI_DP0_OFF (2u)

/** \brief Length for Ifx_RIF_ESI_Bits.DP1 */
#define IFX_RIF_ESI_DP1_LEN (1u)

/** \brief Mask for Ifx_RIF_ESI_Bits.DP1 */
#define IFX_RIF_ESI_DP1_MSK (0x1u)

/** \brief Offset for Ifx_RIF_ESI_Bits.DP1 */
#define IFX_RIF_ESI_DP1_OFF (3u)

/** \brief Length for Ifx_RIF_ESI_Bits.DP2 */
#define IFX_RIF_ESI_DP2_LEN (1u)

/** \brief Mask for Ifx_RIF_ESI_Bits.DP2 */
#define IFX_RIF_ESI_DP2_MSK (0x1u)

/** \brief Offset for Ifx_RIF_ESI_Bits.DP2 */
#define IFX_RIF_ESI_DP2_OFF (4u)

/** \brief Length for Ifx_RIF_ESI_Bits.DP3 */
#define IFX_RIF_ESI_DP3_LEN (1u)

/** \brief Mask for Ifx_RIF_ESI_Bits.DP3 */
#define IFX_RIF_ESI_DP3_MSK (0x1u)

/** \brief Offset for Ifx_RIF_ESI_Bits.DP3 */
#define IFX_RIF_ESI_DP3_OFF (5u)

/** \brief Length for Ifx_RIF_ESI_Bits.CALEN */
#define IFX_RIF_ESI_CALEN_LEN (1u)

/** \brief Mask for Ifx_RIF_ESI_Bits.CALEN */
#define IFX_RIF_ESI_CALEN_MSK (0x1u)

/** \brief Offset for Ifx_RIF_ESI_Bits.CALEN */
#define IFX_RIF_ESI_CALEN_OFF (16u)

/** \brief Length for Ifx_RIF_ESI_Bits.CALBSY */
#define IFX_RIF_ESI_CALBSY_LEN (1u)

/** \brief Mask for Ifx_RIF_ESI_Bits.CALBSY */
#define IFX_RIF_ESI_CALBSY_MSK (0x1u)

/** \brief Offset for Ifx_RIF_ESI_Bits.CALBSY */
#define IFX_RIF_ESI_CALBSY_OFF (17u)

/** \brief Length for Ifx_RIF_ESI_Bits.CALSTAT */
#define IFX_RIF_ESI_CALSTAT_LEN (1u)

/** \brief Mask for Ifx_RIF_ESI_Bits.CALSTAT */
#define IFX_RIF_ESI_CALSTAT_MSK (0x1u)

/** \brief Offset for Ifx_RIF_ESI_Bits.CALSTAT */
#define IFX_RIF_ESI_CALSTAT_OFF (18u)

/** \brief Length for Ifx_RIF_IPI_Bits.DL */
#define IFX_RIF_IPI_DL_LEN (2u)

/** \brief Mask for Ifx_RIF_IPI_Bits.DL */
#define IFX_RIF_IPI_DL_MSK (0x3u)

/** \brief Offset for Ifx_RIF_IPI_Bits.DL */
#define IFX_RIF_IPI_DL_OFF (0u)

/** \brief Length for Ifx_RIF_IPI_Bits.PFP */
#define IFX_RIF_IPI_PFP_LEN (1u)

/** \brief Mask for Ifx_RIF_IPI_Bits.PFP */
#define IFX_RIF_IPI_PFP_MSK (0x1u)

/** \brief Offset for Ifx_RIF_IPI_Bits.PFP */
#define IFX_RIF_IPI_PFP_OFF (3u)

/** \brief Length for Ifx_RIF_IPI_Bits.EN0 */
#define IFX_RIF_IPI_EN0_LEN (1u)

/** \brief Mask for Ifx_RIF_IPI_Bits.EN0 */
#define IFX_RIF_IPI_EN0_MSK (0x1u)

/** \brief Offset for Ifx_RIF_IPI_Bits.EN0 */
#define IFX_RIF_IPI_EN0_OFF (16u)

/** \brief Length for Ifx_RIF_IPI_Bits.EN1 */
#define IFX_RIF_IPI_EN1_LEN (1u)

/** \brief Mask for Ifx_RIF_IPI_Bits.EN1 */
#define IFX_RIF_IPI_EN1_MSK (0x1u)

/** \brief Offset for Ifx_RIF_IPI_Bits.EN1 */
#define IFX_RIF_IPI_EN1_OFF (17u)

/** \brief Length for Ifx_RIF_IPI_Bits.EN2 */
#define IFX_RIF_IPI_EN2_LEN (1u)

/** \brief Mask for Ifx_RIF_IPI_Bits.EN2 */
#define IFX_RIF_IPI_EN2_MSK (0x1u)

/** \brief Offset for Ifx_RIF_IPI_Bits.EN2 */
#define IFX_RIF_IPI_EN2_OFF (18u)

/** \brief Length for Ifx_RIF_IPI_Bits.EN3 */
#define IFX_RIF_IPI_EN3_LEN (1u)

/** \brief Mask for Ifx_RIF_IPI_Bits.EN3 */
#define IFX_RIF_IPI_EN3_MSK (0x1u)

/** \brief Offset for Ifx_RIF_IPI_Bits.EN3 */
#define IFX_RIF_IPI_EN3_OFF (19u)

/** \brief Length for Ifx_RIF_IPI_Bits.SDDV */
#define IFX_RIF_IPI_SDDV_LEN (1u)

/** \brief Mask for Ifx_RIF_IPI_Bits.SDDV */
#define IFX_RIF_IPI_SDDV_MSK (0x1u)

/** \brief Offset for Ifx_RIF_IPI_Bits.SDDV */
#define IFX_RIF_IPI_SDDV_OFF (31u)

/** \brief Length for Ifx_RIF_FLM_Bits.MODE */
#define IFX_RIF_FLM_MODE_LEN (1u)

/** \brief Mask for Ifx_RIF_FLM_Bits.MODE */
#define IFX_RIF_FLM_MODE_MSK (0x1u)

/** \brief Offset for Ifx_RIF_FLM_Bits.MODE */
#define IFX_RIF_FLM_MODE_OFF (0u)

/** \brief Length for Ifx_RIF_FLM_Bits.FSWP */
#define IFX_RIF_FLM_FSWP_LEN (1u)

/** \brief Mask for Ifx_RIF_FLM_Bits.FSWP */
#define IFX_RIF_FLM_FSWP_MSK (0x1u)

/** \brief Offset for Ifx_RIF_FLM_Bits.FSWP */
#define IFX_RIF_FLM_FSWP_OFF (1u)

/** \brief Length for Ifx_RIF_FLM_Bits.CRCEN */
#define IFX_RIF_FLM_CRCEN_LEN (1u)

/** \brief Mask for Ifx_RIF_FLM_Bits.CRCEN */
#define IFX_RIF_FLM_CRCEN_MSK (0x1u)

/** \brief Offset for Ifx_RIF_FLM_Bits.CRCEN */
#define IFX_RIF_FLM_CRCEN_OFF (8u)

/** \brief Length for Ifx_RIF_DMI_Bits.ENF0 */
#define IFX_RIF_DMI_ENF0_LEN (1u)

/** \brief Mask for Ifx_RIF_DMI_Bits.ENF0 */
#define IFX_RIF_DMI_ENF0_MSK (0x1u)

/** \brief Offset for Ifx_RIF_DMI_Bits.ENF0 */
#define IFX_RIF_DMI_ENF0_OFF (0u)

/** \brief Length for Ifx_RIF_DMI_Bits.ENF1 */
#define IFX_RIF_DMI_ENF1_LEN (1u)

/** \brief Mask for Ifx_RIF_DMI_Bits.ENF1 */
#define IFX_RIF_DMI_ENF1_MSK (0x1u)

/** \brief Offset for Ifx_RIF_DMI_Bits.ENF1 */
#define IFX_RIF_DMI_ENF1_OFF (1u)

/** \brief Length for Ifx_RIF_DMI_Bits.ENF2 */
#define IFX_RIF_DMI_ENF2_LEN (1u)

/** \brief Mask for Ifx_RIF_DMI_Bits.ENF2 */
#define IFX_RIF_DMI_ENF2_MSK (0x1u)

/** \brief Offset for Ifx_RIF_DMI_Bits.ENF2 */
#define IFX_RIF_DMI_ENF2_OFF (2u)

/** \brief Length for Ifx_RIF_DMI_Bits.ENF3 */
#define IFX_RIF_DMI_ENF3_LEN (1u)

/** \brief Mask for Ifx_RIF_DMI_Bits.ENF3 */
#define IFX_RIF_DMI_ENF3_MSK (0x1u)

/** \brief Offset for Ifx_RIF_DMI_Bits.ENF3 */
#define IFX_RIF_DMI_ENF3_OFF (3u)

/** \brief Length for Ifx_RIF_RSM0_Bits.R1 */
#define IFX_RIF_RSM0_R1_LEN (4u)

/** \brief Mask for Ifx_RIF_RSM0_Bits.R1 */
#define IFX_RIF_RSM0_R1_MSK (0xfu)

/** \brief Offset for Ifx_RIF_RSM0_Bits.R1 */
#define IFX_RIF_RSM0_R1_OFF (0u)

/** \brief Length for Ifx_RIF_RSM0_Bits.R3 */
#define IFX_RIF_RSM0_R3_LEN (4u)

/** \brief Mask for Ifx_RIF_RSM0_Bits.R3 */
#define IFX_RIF_RSM0_R3_MSK (0xfu)

/** \brief Offset for Ifx_RIF_RSM0_Bits.R3 */
#define IFX_RIF_RSM0_R3_OFF (8u)

/** \brief Length for Ifx_RIF_RSM0_Bits.WAIT */
#define IFX_RIF_RSM0_WAIT_LEN (4u)

/** \brief Mask for Ifx_RIF_RSM0_Bits.WAIT */
#define IFX_RIF_RSM0_WAIT_MSK (0xfu)

/** \brief Offset for Ifx_RIF_RSM0_Bits.WAIT */
#define IFX_RIF_RSM0_WAIT_OFF (12u)

/** \brief Length for Ifx_RIF_RSM0_Bits.PAUSE */
#define IFX_RIF_RSM0_PAUSE_LEN (4u)

/** \brief Mask for Ifx_RIF_RSM0_Bits.PAUSE */
#define IFX_RIF_RSM0_PAUSE_MSK (0xfu)

/** \brief Offset for Ifx_RIF_RSM0_Bits.PAUSE */
#define IFX_RIF_RSM0_PAUSE_OFF (16u)

/** \brief Length for Ifx_RIF_RSM0_Bits.PRE */
#define IFX_RIF_RSM0_PRE_LEN (6u)

/** \brief Mask for Ifx_RIF_RSM0_Bits.PRE */
#define IFX_RIF_RSM0_PRE_MSK (0x3fu)

/** \brief Offset for Ifx_RIF_RSM0_Bits.PRE */
#define IFX_RIF_RSM0_PRE_OFF (24u)

/** \brief Length for Ifx_RIF_RSM0_Bits.LCKSTP */
#define IFX_RIF_RSM0_LCKSTP_LEN (1u)

/** \brief Mask for Ifx_RIF_RSM0_Bits.LCKSTP */
#define IFX_RIF_RSM0_LCKSTP_MSK (0x1u)

/** \brief Offset for Ifx_RIF_RSM0_Bits.LCKSTP */
#define IFX_RIF_RSM0_LCKSTP_OFF (30u)

/** \brief Length for Ifx_RIF_RSM0_Bits.INTADC */
#define IFX_RIF_RSM0_INTADC_LEN (1u)

/** \brief Mask for Ifx_RIF_RSM0_Bits.INTADC */
#define IFX_RIF_RSM0_INTADC_MSK (0x1u)

/** \brief Offset for Ifx_RIF_RSM0_Bits.INTADC */
#define IFX_RIF_RSM0_INTADC_OFF (31u)

/** \brief Length for Ifx_RIF_RSM1_Bits.RAMPS */
#define IFX_RIF_RSM1_RAMPS_LEN (11u)

/** \brief Mask for Ifx_RIF_RSM1_Bits.RAMPS */
#define IFX_RIF_RSM1_RAMPS_MSK (0x7ffu)

/** \brief Offset for Ifx_RIF_RSM1_Bits.RAMPS */
#define IFX_RIF_RSM1_RAMPS_OFF (0u)

/** \brief Length for Ifx_RIF_RSM1_Bits.C1SEL */
#define IFX_RIF_RSM1_C1SEL_LEN (2u)

/** \brief Mask for Ifx_RIF_RSM1_Bits.C1SEL */
#define IFX_RIF_RSM1_C1SEL_MSK (0x3u)

/** \brief Offset for Ifx_RIF_RSM1_Bits.C1SEL */
#define IFX_RIF_RSM1_C1SEL_OFF (12u)

/** \brief Length for Ifx_RIF_RSM1_Bits.R1SEL */
#define IFX_RIF_RSM1_R1SEL_LEN (2u)

/** \brief Mask for Ifx_RIF_RSM1_Bits.R1SEL */
#define IFX_RIF_RSM1_R1SEL_MSK (0x3u)

/** \brief Offset for Ifx_RIF_RSM1_Bits.R1SEL */
#define IFX_RIF_RSM1_R1SEL_OFF (14u)

/** \brief Length for Ifx_RIF_RSM1_Bits.CURRAMP */
#define IFX_RIF_RSM1_CURRAMP_LEN (12u)

/** \brief Mask for Ifx_RIF_RSM1_Bits.CURRAMP */
#define IFX_RIF_RSM1_CURRAMP_MSK (0xfffu)

/** \brief Offset for Ifx_RIF_RSM1_Bits.CURRAMP */
#define IFX_RIF_RSM1_CURRAMP_OFF (16u)

/** \brief Length for Ifx_RIF_RSM1_Bits.C1POL */
#define IFX_RIF_RSM1_C1POL_LEN (1u)

/** \brief Mask for Ifx_RIF_RSM1_Bits.C1POL */
#define IFX_RIF_RSM1_C1POL_MSK (0x1u)

/** \brief Offset for Ifx_RIF_RSM1_Bits.C1POL */
#define IFX_RIF_RSM1_C1POL_OFF (28u)

/** \brief Length for Ifx_RIF_RSM1_Bits.R1POL */
#define IFX_RIF_RSM1_R1POL_LEN (1u)

/** \brief Mask for Ifx_RIF_RSM1_Bits.R1POL */
#define IFX_RIF_RSM1_R1POL_MSK (0x1u)

/** \brief Offset for Ifx_RIF_RSM1_Bits.R1POL */
#define IFX_RIF_RSM1_R1POL_OFF (29u)

/** \brief Length for Ifx_RIF_RSM1_Bits.C1EN */
#define IFX_RIF_RSM1_C1EN_LEN (1u)

/** \brief Mask for Ifx_RIF_RSM1_Bits.C1EN */
#define IFX_RIF_RSM1_C1EN_MSK (0x1u)

/** \brief Offset for Ifx_RIF_RSM1_Bits.C1EN */
#define IFX_RIF_RSM1_C1EN_OFF (30u)

/** \brief Length for Ifx_RIF_RSM1_Bits.R1EN */
#define IFX_RIF_RSM1_R1EN_LEN (1u)

/** \brief Mask for Ifx_RIF_RSM1_Bits.R1EN */
#define IFX_RIF_RSM1_R1EN_MSK (0x1u)

/** \brief Offset for Ifx_RIF_RSM1_Bits.R1EN */
#define IFX_RIF_RSM1_R1EN_OFF (31u)

/** \brief Length for Ifx_RIF_RSM2_Bits.SAMPLES */
#define IFX_RIF_RSM2_SAMPLES_LEN (11u)

/** \brief Mask for Ifx_RIF_RSM2_Bits.SAMPLES */
#define IFX_RIF_RSM2_SAMPLES_MSK (0x7ffu)

/** \brief Offset for Ifx_RIF_RSM2_Bits.SAMPLES */
#define IFX_RIF_RSM2_SAMPLES_OFF (0u)

/** \brief Length for Ifx_RIF_RSM2_Bits.CURSAMPLE */
#define IFX_RIF_RSM2_CURSAMPLE_LEN (12u)

/** \brief Mask for Ifx_RIF_RSM2_Bits.CURSAMPLE */
#define IFX_RIF_RSM2_CURSAMPLE_MSK (0xfffu)

/** \brief Offset for Ifx_RIF_RSM2_Bits.CURSAMPLE */
#define IFX_RIF_RSM2_CURSAMPLE_OFF (16u)

/** \brief Length for Ifx_RIF_INTCON_Bits.CALE */
#define IFX_RIF_INTCON_CALE_LEN (1u)

/** \brief Mask for Ifx_RIF_INTCON_Bits.CALE */
#define IFX_RIF_INTCON_CALE_MSK (0x1u)

/** \brief Offset for Ifx_RIF_INTCON_Bits.CALE */
#define IFX_RIF_INTCON_CALE_OFF (0u)

/** \brief Length for Ifx_RIF_INTCON_Bits.FWE */
#define IFX_RIF_INTCON_FWE_LEN (1u)

/** \brief Mask for Ifx_RIF_INTCON_Bits.FWE */
#define IFX_RIF_INTCON_FWE_MSK (0x1u)

/** \brief Offset for Ifx_RIF_INTCON_Bits.FWE */
#define IFX_RIF_INTCON_FWE_OFF (1u)

/** \brief Length for Ifx_RIF_INTCON_Bits.REE */
#define IFX_RIF_INTCON_REE_LEN (1u)

/** \brief Mask for Ifx_RIF_INTCON_Bits.REE */
#define IFX_RIF_INTCON_REE_MSK (0x1u)

/** \brief Offset for Ifx_RIF_INTCON_Bits.REE */
#define IFX_RIF_INTCON_REE_OFF (2u)

/** \brief Length for Ifx_RIF_INTCON_Bits.CEE */
#define IFX_RIF_INTCON_CEE_LEN (1u)

/** \brief Mask for Ifx_RIF_INTCON_Bits.CEE */
#define IFX_RIF_INTCON_CEE_MSK (0x1u)

/** \brief Offset for Ifx_RIF_INTCON_Bits.CEE */
#define IFX_RIF_INTCON_CEE_OFF (3u)

/** \brief Length for Ifx_RIF_INTCON_Bits.CRCE0 */
#define IFX_RIF_INTCON_CRCE0_LEN (1u)

/** \brief Mask for Ifx_RIF_INTCON_Bits.CRCE0 */
#define IFX_RIF_INTCON_CRCE0_MSK (0x1u)

/** \brief Offset for Ifx_RIF_INTCON_Bits.CRCE0 */
#define IFX_RIF_INTCON_CRCE0_OFF (4u)

/** \brief Length for Ifx_RIF_INTCON_Bits.CRCE1 */
#define IFX_RIF_INTCON_CRCE1_LEN (1u)

/** \brief Mask for Ifx_RIF_INTCON_Bits.CRCE1 */
#define IFX_RIF_INTCON_CRCE1_MSK (0x1u)

/** \brief Offset for Ifx_RIF_INTCON_Bits.CRCE1 */
#define IFX_RIF_INTCON_CRCE1_OFF (5u)

/** \brief Length for Ifx_RIF_INTCON_Bits.CRCE2 */
#define IFX_RIF_INTCON_CRCE2_LEN (1u)

/** \brief Mask for Ifx_RIF_INTCON_Bits.CRCE2 */
#define IFX_RIF_INTCON_CRCE2_MSK (0x1u)

/** \brief Offset for Ifx_RIF_INTCON_Bits.CRCE2 */
#define IFX_RIF_INTCON_CRCE2_OFF (6u)

/** \brief Length for Ifx_RIF_INTCON_Bits.CRCE3 */
#define IFX_RIF_INTCON_CRCE3_LEN (1u)

/** \brief Mask for Ifx_RIF_INTCON_Bits.CRCE3 */
#define IFX_RIF_INTCON_CRCE3_MSK (0x1u)

/** \brief Offset for Ifx_RIF_INTCON_Bits.CRCE3 */
#define IFX_RIF_INTCON_CRCE3_OFF (7u)

/** \brief Length for Ifx_RIF_INTCON_Bits.R1EE */
#define IFX_RIF_INTCON_R1EE_LEN (1u)

/** \brief Mask for Ifx_RIF_INTCON_Bits.R1EE */
#define IFX_RIF_INTCON_R1EE_MSK (0x1u)

/** \brief Offset for Ifx_RIF_INTCON_Bits.R1EE */
#define IFX_RIF_INTCON_R1EE_OFF (8u)

/** \brief Length for Ifx_RIF_INTCON_Bits.C1EE */
#define IFX_RIF_INTCON_C1EE_LEN (1u)

/** \brief Mask for Ifx_RIF_INTCON_Bits.C1EE */
#define IFX_RIF_INTCON_C1EE_MSK (0x1u)

/** \brief Offset for Ifx_RIF_INTCON_Bits.C1EE */
#define IFX_RIF_INTCON_C1EE_OFF (9u)

/** \brief Length for Ifx_RIF_INTCON_Bits.R1SE */
#define IFX_RIF_INTCON_R1SE_LEN (1u)

/** \brief Mask for Ifx_RIF_INTCON_Bits.R1SE */
#define IFX_RIF_INTCON_R1SE_MSK (0x1u)

/** \brief Offset for Ifx_RIF_INTCON_Bits.R1SE */
#define IFX_RIF_INTCON_R1SE_OFF (10u)

/** \brief Length for Ifx_RIF_INTCON_Bits.CALF */
#define IFX_RIF_INTCON_CALF_LEN (1u)

/** \brief Mask for Ifx_RIF_INTCON_Bits.CALF */
#define IFX_RIF_INTCON_CALF_MSK (0x1u)

/** \brief Offset for Ifx_RIF_INTCON_Bits.CALF */
#define IFX_RIF_INTCON_CALF_OFF (16u)

/** \brief Length for Ifx_RIF_INTCON_Bits.FWF */
#define IFX_RIF_INTCON_FWF_LEN (1u)

/** \brief Mask for Ifx_RIF_INTCON_Bits.FWF */
#define IFX_RIF_INTCON_FWF_MSK (0x1u)

/** \brief Offset for Ifx_RIF_INTCON_Bits.FWF */
#define IFX_RIF_INTCON_FWF_OFF (17u)

/** \brief Length for Ifx_RIF_INTCON_Bits.REF */
#define IFX_RIF_INTCON_REF_LEN (1u)

/** \brief Mask for Ifx_RIF_INTCON_Bits.REF */
#define IFX_RIF_INTCON_REF_MSK (0x1u)

/** \brief Offset for Ifx_RIF_INTCON_Bits.REF */
#define IFX_RIF_INTCON_REF_OFF (18u)

/** \brief Length for Ifx_RIF_INTCON_Bits.CEF */
#define IFX_RIF_INTCON_CEF_LEN (1u)

/** \brief Mask for Ifx_RIF_INTCON_Bits.CEF */
#define IFX_RIF_INTCON_CEF_MSK (0x1u)

/** \brief Offset for Ifx_RIF_INTCON_Bits.CEF */
#define IFX_RIF_INTCON_CEF_OFF (19u)

/** \brief Length for Ifx_RIF_INTCON_Bits.CRCF0 */
#define IFX_RIF_INTCON_CRCF0_LEN (1u)

/** \brief Mask for Ifx_RIF_INTCON_Bits.CRCF0 */
#define IFX_RIF_INTCON_CRCF0_MSK (0x1u)

/** \brief Offset for Ifx_RIF_INTCON_Bits.CRCF0 */
#define IFX_RIF_INTCON_CRCF0_OFF (20u)

/** \brief Length for Ifx_RIF_INTCON_Bits.CRCF1 */
#define IFX_RIF_INTCON_CRCF1_LEN (1u)

/** \brief Mask for Ifx_RIF_INTCON_Bits.CRCF1 */
#define IFX_RIF_INTCON_CRCF1_MSK (0x1u)

/** \brief Offset for Ifx_RIF_INTCON_Bits.CRCF1 */
#define IFX_RIF_INTCON_CRCF1_OFF (21u)

/** \brief Length for Ifx_RIF_INTCON_Bits.CRCF2 */
#define IFX_RIF_INTCON_CRCF2_LEN (1u)

/** \brief Mask for Ifx_RIF_INTCON_Bits.CRCF2 */
#define IFX_RIF_INTCON_CRCF2_MSK (0x1u)

/** \brief Offset for Ifx_RIF_INTCON_Bits.CRCF2 */
#define IFX_RIF_INTCON_CRCF2_OFF (22u)

/** \brief Length for Ifx_RIF_INTCON_Bits.CRCF3 */
#define IFX_RIF_INTCON_CRCF3_LEN (1u)

/** \brief Mask for Ifx_RIF_INTCON_Bits.CRCF3 */
#define IFX_RIF_INTCON_CRCF3_MSK (0x1u)

/** \brief Offset for Ifx_RIF_INTCON_Bits.CRCF3 */
#define IFX_RIF_INTCON_CRCF3_OFF (23u)

/** \brief Length for Ifx_RIF_INTCON_Bits.R1EF */
#define IFX_RIF_INTCON_R1EF_LEN (1u)

/** \brief Mask for Ifx_RIF_INTCON_Bits.R1EF */
#define IFX_RIF_INTCON_R1EF_MSK (0x1u)

/** \brief Offset for Ifx_RIF_INTCON_Bits.R1EF */
#define IFX_RIF_INTCON_R1EF_OFF (24u)

/** \brief Length for Ifx_RIF_INTCON_Bits.C1EF */
#define IFX_RIF_INTCON_C1EF_LEN (1u)

/** \brief Mask for Ifx_RIF_INTCON_Bits.C1EF */
#define IFX_RIF_INTCON_C1EF_MSK (0x1u)

/** \brief Offset for Ifx_RIF_INTCON_Bits.C1EF */
#define IFX_RIF_INTCON_C1EF_OFF (25u)

/** \brief Length for Ifx_RIF_INTCON_Bits.R1SF */
#define IFX_RIF_INTCON_R1SF_LEN (1u)

/** \brief Mask for Ifx_RIF_INTCON_Bits.R1SF */
#define IFX_RIF_INTCON_R1SF_MSK (0x1u)

/** \brief Offset for Ifx_RIF_INTCON_Bits.R1SF */
#define IFX_RIF_INTCON_R1SF_OFF (26u)

/** \brief Length for Ifx_RIF_FLAGSSET_Bits.CALS */
#define IFX_RIF_FLAGSSET_CALS_LEN (1u)

/** \brief Mask for Ifx_RIF_FLAGSSET_Bits.CALS */
#define IFX_RIF_FLAGSSET_CALS_MSK (0x1u)

/** \brief Offset for Ifx_RIF_FLAGSSET_Bits.CALS */
#define IFX_RIF_FLAGSSET_CALS_OFF (16u)

/** \brief Length for Ifx_RIF_FLAGSSET_Bits.FWS */
#define IFX_RIF_FLAGSSET_FWS_LEN (1u)

/** \brief Mask for Ifx_RIF_FLAGSSET_Bits.FWS */
#define IFX_RIF_FLAGSSET_FWS_MSK (0x1u)

/** \brief Offset for Ifx_RIF_FLAGSSET_Bits.FWS */
#define IFX_RIF_FLAGSSET_FWS_OFF (17u)

/** \brief Length for Ifx_RIF_FLAGSSET_Bits.RES */
#define IFX_RIF_FLAGSSET_RES_LEN (1u)

/** \brief Mask for Ifx_RIF_FLAGSSET_Bits.RES */
#define IFX_RIF_FLAGSSET_RES_MSK (0x1u)

/** \brief Offset for Ifx_RIF_FLAGSSET_Bits.RES */
#define IFX_RIF_FLAGSSET_RES_OFF (18u)

/** \brief Length for Ifx_RIF_FLAGSSET_Bits.CES */
#define IFX_RIF_FLAGSSET_CES_LEN (1u)

/** \brief Mask for Ifx_RIF_FLAGSSET_Bits.CES */
#define IFX_RIF_FLAGSSET_CES_MSK (0x1u)

/** \brief Offset for Ifx_RIF_FLAGSSET_Bits.CES */
#define IFX_RIF_FLAGSSET_CES_OFF (19u)

/** \brief Length for Ifx_RIF_FLAGSSET_Bits.CRCS0 */
#define IFX_RIF_FLAGSSET_CRCS0_LEN (1u)

/** \brief Mask for Ifx_RIF_FLAGSSET_Bits.CRCS0 */
#define IFX_RIF_FLAGSSET_CRCS0_MSK (0x1u)

/** \brief Offset for Ifx_RIF_FLAGSSET_Bits.CRCS0 */
#define IFX_RIF_FLAGSSET_CRCS0_OFF (20u)

/** \brief Length for Ifx_RIF_FLAGSSET_Bits.CRCS1 */
#define IFX_RIF_FLAGSSET_CRCS1_LEN (1u)

/** \brief Mask for Ifx_RIF_FLAGSSET_Bits.CRCS1 */
#define IFX_RIF_FLAGSSET_CRCS1_MSK (0x1u)

/** \brief Offset for Ifx_RIF_FLAGSSET_Bits.CRCS1 */
#define IFX_RIF_FLAGSSET_CRCS1_OFF (21u)

/** \brief Length for Ifx_RIF_FLAGSSET_Bits.CRCS2 */
#define IFX_RIF_FLAGSSET_CRCS2_LEN (1u)

/** \brief Mask for Ifx_RIF_FLAGSSET_Bits.CRCS2 */
#define IFX_RIF_FLAGSSET_CRCS2_MSK (0x1u)

/** \brief Offset for Ifx_RIF_FLAGSSET_Bits.CRCS2 */
#define IFX_RIF_FLAGSSET_CRCS2_OFF (22u)

/** \brief Length for Ifx_RIF_FLAGSSET_Bits.CRCS3 */
#define IFX_RIF_FLAGSSET_CRCS3_LEN (1u)

/** \brief Mask for Ifx_RIF_FLAGSSET_Bits.CRCS3 */
#define IFX_RIF_FLAGSSET_CRCS3_MSK (0x1u)

/** \brief Offset for Ifx_RIF_FLAGSSET_Bits.CRCS3 */
#define IFX_RIF_FLAGSSET_CRCS3_OFF (23u)

/** \brief Length for Ifx_RIF_FLAGSSET_Bits.R1ES */
#define IFX_RIF_FLAGSSET_R1ES_LEN (1u)

/** \brief Mask for Ifx_RIF_FLAGSSET_Bits.R1ES */
#define IFX_RIF_FLAGSSET_R1ES_MSK (0x1u)

/** \brief Offset for Ifx_RIF_FLAGSSET_Bits.R1ES */
#define IFX_RIF_FLAGSSET_R1ES_OFF (24u)

/** \brief Length for Ifx_RIF_FLAGSSET_Bits.C1ES */
#define IFX_RIF_FLAGSSET_C1ES_LEN (1u)

/** \brief Mask for Ifx_RIF_FLAGSSET_Bits.C1ES */
#define IFX_RIF_FLAGSSET_C1ES_MSK (0x1u)

/** \brief Offset for Ifx_RIF_FLAGSSET_Bits.C1ES */
#define IFX_RIF_FLAGSSET_C1ES_OFF (25u)

/** \brief Length for Ifx_RIF_FLAGSSET_Bits.R1SS */
#define IFX_RIF_FLAGSSET_R1SS_LEN (1u)

/** \brief Mask for Ifx_RIF_FLAGSSET_Bits.R1SS */
#define IFX_RIF_FLAGSSET_R1SS_MSK (0x1u)

/** \brief Offset for Ifx_RIF_FLAGSSET_Bits.R1SS */
#define IFX_RIF_FLAGSSET_R1SS_OFF (26u)

/** \brief Length for Ifx_RIF_FLAGSCL_Bits.CALC */
#define IFX_RIF_FLAGSCL_CALC_LEN (1u)

/** \brief Mask for Ifx_RIF_FLAGSCL_Bits.CALC */
#define IFX_RIF_FLAGSCL_CALC_MSK (0x1u)

/** \brief Offset for Ifx_RIF_FLAGSCL_Bits.CALC */
#define IFX_RIF_FLAGSCL_CALC_OFF (16u)

/** \brief Length for Ifx_RIF_FLAGSCL_Bits.FWC */
#define IFX_RIF_FLAGSCL_FWC_LEN (1u)

/** \brief Mask for Ifx_RIF_FLAGSCL_Bits.FWC */
#define IFX_RIF_FLAGSCL_FWC_MSK (0x1u)

/** \brief Offset for Ifx_RIF_FLAGSCL_Bits.FWC */
#define IFX_RIF_FLAGSCL_FWC_OFF (17u)

/** \brief Length for Ifx_RIF_FLAGSCL_Bits.REC */
#define IFX_RIF_FLAGSCL_REC_LEN (1u)

/** \brief Mask for Ifx_RIF_FLAGSCL_Bits.REC */
#define IFX_RIF_FLAGSCL_REC_MSK (0x1u)

/** \brief Offset for Ifx_RIF_FLAGSCL_Bits.REC */
#define IFX_RIF_FLAGSCL_REC_OFF (18u)

/** \brief Length for Ifx_RIF_FLAGSCL_Bits.CEC */
#define IFX_RIF_FLAGSCL_CEC_LEN (1u)

/** \brief Mask for Ifx_RIF_FLAGSCL_Bits.CEC */
#define IFX_RIF_FLAGSCL_CEC_MSK (0x1u)

/** \brief Offset for Ifx_RIF_FLAGSCL_Bits.CEC */
#define IFX_RIF_FLAGSCL_CEC_OFF (19u)

/** \brief Length for Ifx_RIF_FLAGSCL_Bits.CRCC0 */
#define IFX_RIF_FLAGSCL_CRCC0_LEN (1u)

/** \brief Mask for Ifx_RIF_FLAGSCL_Bits.CRCC0 */
#define IFX_RIF_FLAGSCL_CRCC0_MSK (0x1u)

/** \brief Offset for Ifx_RIF_FLAGSCL_Bits.CRCC0 */
#define IFX_RIF_FLAGSCL_CRCC0_OFF (20u)

/** \brief Length for Ifx_RIF_FLAGSCL_Bits.CRCC1 */
#define IFX_RIF_FLAGSCL_CRCC1_LEN (1u)

/** \brief Mask for Ifx_RIF_FLAGSCL_Bits.CRCC1 */
#define IFX_RIF_FLAGSCL_CRCC1_MSK (0x1u)

/** \brief Offset for Ifx_RIF_FLAGSCL_Bits.CRCC1 */
#define IFX_RIF_FLAGSCL_CRCC1_OFF (21u)

/** \brief Length for Ifx_RIF_FLAGSCL_Bits.CRCC2 */
#define IFX_RIF_FLAGSCL_CRCC2_LEN (1u)

/** \brief Mask for Ifx_RIF_FLAGSCL_Bits.CRCC2 */
#define IFX_RIF_FLAGSCL_CRCC2_MSK (0x1u)

/** \brief Offset for Ifx_RIF_FLAGSCL_Bits.CRCC2 */
#define IFX_RIF_FLAGSCL_CRCC2_OFF (22u)

/** \brief Length for Ifx_RIF_FLAGSCL_Bits.CRCC3 */
#define IFX_RIF_FLAGSCL_CRCC3_LEN (1u)

/** \brief Mask for Ifx_RIF_FLAGSCL_Bits.CRCC3 */
#define IFX_RIF_FLAGSCL_CRCC3_MSK (0x1u)

/** \brief Offset for Ifx_RIF_FLAGSCL_Bits.CRCC3 */
#define IFX_RIF_FLAGSCL_CRCC3_OFF (23u)

/** \brief Length for Ifx_RIF_FLAGSCL_Bits.R1EC */
#define IFX_RIF_FLAGSCL_R1EC_LEN (1u)

/** \brief Mask for Ifx_RIF_FLAGSCL_Bits.R1EC */
#define IFX_RIF_FLAGSCL_R1EC_MSK (0x1u)

/** \brief Offset for Ifx_RIF_FLAGSCL_Bits.R1EC */
#define IFX_RIF_FLAGSCL_R1EC_OFF (24u)

/** \brief Length for Ifx_RIF_FLAGSCL_Bits.C1EC */
#define IFX_RIF_FLAGSCL_C1EC_LEN (1u)

/** \brief Mask for Ifx_RIF_FLAGSCL_Bits.C1EC */
#define IFX_RIF_FLAGSCL_C1EC_MSK (0x1u)

/** \brief Offset for Ifx_RIF_FLAGSCL_Bits.C1EC */
#define IFX_RIF_FLAGSCL_C1EC_OFF (25u)

/** \brief Length for Ifx_RIF_FLAGSCL_Bits.R1SC */
#define IFX_RIF_FLAGSCL_R1SC_LEN (1u)

/** \brief Mask for Ifx_RIF_FLAGSCL_Bits.R1SC */
#define IFX_RIF_FLAGSCL_R1SC_MSK (0x1u)

/** \brief Offset for Ifx_RIF_FLAGSCL_Bits.R1SC */
#define IFX_RIF_FLAGSCL_R1SC_OFF (26u)

/** \brief Length for Ifx_RIF_FWDG_Bits.THRESHOLD */
#define IFX_RIF_FWDG_THRESHOLD_LEN (10u)

/** \brief Mask for Ifx_RIF_FWDG_Bits.THRESHOLD */
#define IFX_RIF_FWDG_THRESHOLD_MSK (0x3ffu)

/** \brief Offset for Ifx_RIF_FWDG_Bits.THRESHOLD */
#define IFX_RIF_FWDG_THRESHOLD_OFF (0u)

/** \brief Length for Ifx_RIF_DFU_Bits.DF */
#define IFX_RIF_DFU_DF_LEN (1u)

/** \brief Mask for Ifx_RIF_DFU_Bits.DF */
#define IFX_RIF_DFU_DF_MSK (0x1u)

/** \brief Offset for Ifx_RIF_DFU_Bits.DF */
#define IFX_RIF_DFU_DF_OFF (0u)

/** \brief Length for Ifx_RIF_DFU_Bits.DA */
#define IFX_RIF_DFU_DA_LEN (1u)

/** \brief Mask for Ifx_RIF_DFU_Bits.DA */
#define IFX_RIF_DFU_DA_MSK (0x1u)

/** \brief Offset for Ifx_RIF_DFU_Bits.DA */
#define IFX_RIF_DFU_DA_OFF (1u)

/** \brief Length for Ifx_RIF_DFU_Bits.MSB */
#define IFX_RIF_DFU_MSB_LEN (1u)

/** \brief Mask for Ifx_RIF_DFU_Bits.MSB */
#define IFX_RIF_DFU_MSB_MSK (0x1u)

/** \brief Offset for Ifx_RIF_DFU_Bits.MSB */
#define IFX_RIF_DFU_MSB_OFF (2u)

/** \brief Length for Ifx_RIF_SRIFOVRCFG_Bits.SKMR */
#define IFX_RIF_SRIFOVRCFG_SKMR_LEN (2u)

/** \brief Mask for Ifx_RIF_SRIFOVRCFG_Bits.SKMR */
#define IFX_RIF_SRIFOVRCFG_SKMR_MSK (0x3u)

/** \brief Offset for Ifx_RIF_SRIFOVRCFG_Bits.SKMR */
#define IFX_RIF_SRIFOVRCFG_SKMR_OFF (0u)

/** \brief Length for Ifx_RIF_RSM2CAP_Bits.ENDSAMPLE */
#define IFX_RIF_RSM2CAP_ENDSAMPLE_LEN (12u)

/** \brief Mask for Ifx_RIF_RSM2CAP_Bits.ENDSAMPLE */
#define IFX_RIF_RSM2CAP_ENDSAMPLE_MSK (0xfffu)

/** \brief Offset for Ifx_RIF_RSM2CAP_Bits.ENDSAMPLE */
#define IFX_RIF_RSM2CAP_ENDSAMPLE_OFF (16u)

/** \brief Length for Ifx_RIF_LVDSCON0_Bits.FRAME */
#define IFX_RIF_LVDSCON0_FRAME_LEN (8u)

/** \brief Mask for Ifx_RIF_LVDSCON0_Bits.FRAME */
#define IFX_RIF_LVDSCON0_FRAME_MSK (0xffu)

/** \brief Offset for Ifx_RIF_LVDSCON0_Bits.FRAME */
#define IFX_RIF_LVDSCON0_FRAME_OFF (0u)

/** \brief Length for Ifx_RIF_LVDSCON0_Bits.CLK */
#define IFX_RIF_LVDSCON0_CLK_LEN (8u)

/** \brief Mask for Ifx_RIF_LVDSCON0_Bits.CLK */
#define IFX_RIF_LVDSCON0_CLK_MSK (0xffu)

/** \brief Offset for Ifx_RIF_LVDSCON0_Bits.CLK */
#define IFX_RIF_LVDSCON0_CLK_OFF (8u)

/** \brief Length for Ifx_RIF_LVDSCON0_Bits.DATA0 */
#define IFX_RIF_LVDSCON0_DATA0_LEN (8u)

/** \brief Mask for Ifx_RIF_LVDSCON0_Bits.DATA0 */
#define IFX_RIF_LVDSCON0_DATA0_MSK (0xffu)

/** \brief Offset for Ifx_RIF_LVDSCON0_Bits.DATA0 */
#define IFX_RIF_LVDSCON0_DATA0_OFF (16u)

/** \brief Length for Ifx_RIF_LVDSCON0_Bits.DATA1 */
#define IFX_RIF_LVDSCON0_DATA1_LEN (8u)

/** \brief Mask for Ifx_RIF_LVDSCON0_Bits.DATA1 */
#define IFX_RIF_LVDSCON0_DATA1_MSK (0xffu)

/** \brief Offset for Ifx_RIF_LVDSCON0_Bits.DATA1 */
#define IFX_RIF_LVDSCON0_DATA1_OFF (24u)

/** \brief Length for Ifx_RIF_LVDSCON1_Bits.DATA2 */
#define IFX_RIF_LVDSCON1_DATA2_LEN (8u)

/** \brief Mask for Ifx_RIF_LVDSCON1_Bits.DATA2 */
#define IFX_RIF_LVDSCON1_DATA2_MSK (0xffu)

/** \brief Offset for Ifx_RIF_LVDSCON1_Bits.DATA2 */
#define IFX_RIF_LVDSCON1_DATA2_OFF (0u)

/** \brief Length for Ifx_RIF_LVDSCON1_Bits.DATA3 */
#define IFX_RIF_LVDSCON1_DATA3_LEN (8u)

/** \brief Mask for Ifx_RIF_LVDSCON1_Bits.DATA3 */
#define IFX_RIF_LVDSCON1_DATA3_MSK (0xffu)

/** \brief Offset for Ifx_RIF_LVDSCON1_Bits.DATA3 */
#define IFX_RIF_LVDSCON1_DATA3_OFF (8u)

/** \brief Length for Ifx_RIF_LVDSCON1_Bits.MISC */
#define IFX_RIF_LVDSCON1_MISC_LEN (3u)

/** \brief Mask for Ifx_RIF_LVDSCON1_Bits.MISC */
#define IFX_RIF_LVDSCON1_MISC_MSK (0x7u)

/** \brief Offset for Ifx_RIF_LVDSCON1_Bits.MISC */
#define IFX_RIF_LVDSCON1_MISC_OFF (16u)

/** \brief Length for Ifx_RIF_LVDSCON1_Bits.RTERM */
#define IFX_RIF_LVDSCON1_RTERM_LEN (3u)

/** \brief Mask for Ifx_RIF_LVDSCON1_Bits.RTERM */
#define IFX_RIF_LVDSCON1_RTERM_MSK (0x7u)

/** \brief Offset for Ifx_RIF_LVDSCON1_Bits.RTERM */
#define IFX_RIF_LVDSCON1_RTERM_OFF (19u)

/** \brief Length for Ifx_RIF_LVDSCON1_Bits.PWRDN */
#define IFX_RIF_LVDSCON1_PWRDN_LEN (1u)

/** \brief Mask for Ifx_RIF_LVDSCON1_Bits.PWRDN */
#define IFX_RIF_LVDSCON1_PWRDN_MSK (0x1u)

/** \brief Offset for Ifx_RIF_LVDSCON1_Bits.PWRDN */
#define IFX_RIF_LVDSCON1_PWRDN_OFF (24u)

/** \brief Length for Ifx_RIF_LVDSCON1_Bits.LVDS5VEN */
#define IFX_RIF_LVDSCON1_LVDS5VEN_LEN (1u)

/** \brief Mask for Ifx_RIF_LVDSCON1_Bits.LVDS5VEN */
#define IFX_RIF_LVDSCON1_LVDS5VEN_MSK (0x1u)

/** \brief Offset for Ifx_RIF_LVDSCON1_Bits.LVDS5VEN */
#define IFX_RIF_LVDSCON1_LVDS5VEN_OFF (25u)

/** \brief Length for Ifx_RIF_DBGDLY0_Bits.FDLY0 */
#define IFX_RIF_DBGDLY0_FDLY0_LEN (3u)

/** \brief Mask for Ifx_RIF_DBGDLY0_Bits.FDLY0 */
#define IFX_RIF_DBGDLY0_FDLY0_MSK (0x7u)

/** \brief Offset for Ifx_RIF_DBGDLY0_Bits.FDLY0 */
#define IFX_RIF_DBGDLY0_FDLY0_OFF (0u)

/** \brief Length for Ifx_RIF_DBGDLY0_Bits.CDLY0 */
#define IFX_RIF_DBGDLY0_CDLY0_LEN (3u)

/** \brief Mask for Ifx_RIF_DBGDLY0_Bits.CDLY0 */
#define IFX_RIF_DBGDLY0_CDLY0_MSK (0x7u)

/** \brief Offset for Ifx_RIF_DBGDLY0_Bits.CDLY0 */
#define IFX_RIF_DBGDLY0_CDLY0_OFF (4u)

/** \brief Length for Ifx_RIF_DBGDLY0_Bits.DDLY0 */
#define IFX_RIF_DBGDLY0_DDLY0_LEN (3u)

/** \brief Mask for Ifx_RIF_DBGDLY0_Bits.DDLY0 */
#define IFX_RIF_DBGDLY0_DDLY0_MSK (0x7u)

/** \brief Offset for Ifx_RIF_DBGDLY0_Bits.DDLY0 */
#define IFX_RIF_DBGDLY0_DDLY0_OFF (8u)

/** \brief Length for Ifx_RIF_DBGDLY0_Bits.FDLY1 */
#define IFX_RIF_DBGDLY0_FDLY1_LEN (3u)

/** \brief Mask for Ifx_RIF_DBGDLY0_Bits.FDLY1 */
#define IFX_RIF_DBGDLY0_FDLY1_MSK (0x7u)

/** \brief Offset for Ifx_RIF_DBGDLY0_Bits.FDLY1 */
#define IFX_RIF_DBGDLY0_FDLY1_OFF (12u)

/** \brief Length for Ifx_RIF_DBGDLY0_Bits.CDLY1 */
#define IFX_RIF_DBGDLY0_CDLY1_LEN (3u)

/** \brief Mask for Ifx_RIF_DBGDLY0_Bits.CDLY1 */
#define IFX_RIF_DBGDLY0_CDLY1_MSK (0x7u)

/** \brief Offset for Ifx_RIF_DBGDLY0_Bits.CDLY1 */
#define IFX_RIF_DBGDLY0_CDLY1_OFF (16u)

/** \brief Length for Ifx_RIF_DBGDLY0_Bits.DDLY1 */
#define IFX_RIF_DBGDLY0_DDLY1_LEN (3u)

/** \brief Mask for Ifx_RIF_DBGDLY0_Bits.DDLY1 */
#define IFX_RIF_DBGDLY0_DDLY1_MSK (0x7u)

/** \brief Offset for Ifx_RIF_DBGDLY0_Bits.DDLY1 */
#define IFX_RIF_DBGDLY0_DDLY1_OFF (20u)

/** \brief Length for Ifx_RIF_DBGDLY1_Bits.FDLY2 */
#define IFX_RIF_DBGDLY1_FDLY2_LEN (3u)

/** \brief Mask for Ifx_RIF_DBGDLY1_Bits.FDLY2 */
#define IFX_RIF_DBGDLY1_FDLY2_MSK (0x7u)

/** \brief Offset for Ifx_RIF_DBGDLY1_Bits.FDLY2 */
#define IFX_RIF_DBGDLY1_FDLY2_OFF (0u)

/** \brief Length for Ifx_RIF_DBGDLY1_Bits.CDLY2 */
#define IFX_RIF_DBGDLY1_CDLY2_LEN (3u)

/** \brief Mask for Ifx_RIF_DBGDLY1_Bits.CDLY2 */
#define IFX_RIF_DBGDLY1_CDLY2_MSK (0x7u)

/** \brief Offset for Ifx_RIF_DBGDLY1_Bits.CDLY2 */
#define IFX_RIF_DBGDLY1_CDLY2_OFF (4u)

/** \brief Length for Ifx_RIF_DBGDLY1_Bits.DDLY2 */
#define IFX_RIF_DBGDLY1_DDLY2_LEN (3u)

/** \brief Mask for Ifx_RIF_DBGDLY1_Bits.DDLY2 */
#define IFX_RIF_DBGDLY1_DDLY2_MSK (0x7u)

/** \brief Offset for Ifx_RIF_DBGDLY1_Bits.DDLY2 */
#define IFX_RIF_DBGDLY1_DDLY2_OFF (8u)

/** \brief Length for Ifx_RIF_DBGDLY1_Bits.FDLY3 */
#define IFX_RIF_DBGDLY1_FDLY3_LEN (3u)

/** \brief Mask for Ifx_RIF_DBGDLY1_Bits.FDLY3 */
#define IFX_RIF_DBGDLY1_FDLY3_MSK (0x7u)

/** \brief Offset for Ifx_RIF_DBGDLY1_Bits.FDLY3 */
#define IFX_RIF_DBGDLY1_FDLY3_OFF (12u)

/** \brief Length for Ifx_RIF_DBGDLY1_Bits.CDLY3 */
#define IFX_RIF_DBGDLY1_CDLY3_LEN (3u)

/** \brief Mask for Ifx_RIF_DBGDLY1_Bits.CDLY3 */
#define IFX_RIF_DBGDLY1_CDLY3_MSK (0x7u)

/** \brief Offset for Ifx_RIF_DBGDLY1_Bits.CDLY3 */
#define IFX_RIF_DBGDLY1_CDLY3_OFF (16u)

/** \brief Length for Ifx_RIF_DBGDLY1_Bits.DDLY3 */
#define IFX_RIF_DBGDLY1_DDLY3_LEN (3u)

/** \brief Mask for Ifx_RIF_DBGDLY1_Bits.DDLY3 */
#define IFX_RIF_DBGDLY1_DDLY3_MSK (0x7u)

/** \brief Offset for Ifx_RIF_DBGDLY1_Bits.DDLY3 */
#define IFX_RIF_DBGDLY1_DDLY3_OFF (20u)

/** \brief Length for Ifx_RIF_DBGDLY1_Bits.BMDLY0 */
#define IFX_RIF_DBGDLY1_BMDLY0_LEN (3u)

/** \brief Mask for Ifx_RIF_DBGDLY1_Bits.BMDLY0 */
#define IFX_RIF_DBGDLY1_BMDLY0_MSK (0x7u)

/** \brief Offset for Ifx_RIF_DBGDLY1_Bits.BMDLY0 */
#define IFX_RIF_DBGDLY1_BMDLY0_OFF (24u)

/** \brief Length for Ifx_RIF_DBGDLY1_Bits.BMDLY1 */
#define IFX_RIF_DBGDLY1_BMDLY1_LEN (3u)

/** \brief Mask for Ifx_RIF_DBGDLY1_Bits.BMDLY1 */
#define IFX_RIF_DBGDLY1_BMDLY1_MSK (0x7u)

/** \brief Offset for Ifx_RIF_DBGDLY1_Bits.BMDLY1 */
#define IFX_RIF_DBGDLY1_BMDLY1_OFF (28u)

/** \brief Length for Ifx_RIF_DBG0_Bits.DD1 */
#define IFX_RIF_DBG0_DD1_LEN (16u)

/** \brief Mask for Ifx_RIF_DBG0_Bits.DD1 */
#define IFX_RIF_DBG0_DD1_MSK (0xffffu)

/** \brief Offset for Ifx_RIF_DBG0_Bits.DD1 */
#define IFX_RIF_DBG0_DD1_OFF (0u)

/** \brief Length for Ifx_RIF_DBG0_Bits.DD2 */
#define IFX_RIF_DBG0_DD2_LEN (16u)

/** \brief Mask for Ifx_RIF_DBG0_Bits.DD2 */
#define IFX_RIF_DBG0_DD2_MSK (0xffffu)

/** \brief Offset for Ifx_RIF_DBG0_Bits.DD2 */
#define IFX_RIF_DBG0_DD2_OFF (16u)

/** \brief Length for Ifx_RIF_DBG1_Bits.DD3 */
#define IFX_RIF_DBG1_DD3_LEN (16u)

/** \brief Mask for Ifx_RIF_DBG1_Bits.DD3 */
#define IFX_RIF_DBG1_DD3_MSK (0xffffu)

/** \brief Offset for Ifx_RIF_DBG1_Bits.DD3 */
#define IFX_RIF_DBG1_DD3_OFF (0u)

/** \brief Length for Ifx_RIF_DBG1_Bits.DD4 */
#define IFX_RIF_DBG1_DD4_LEN (16u)

/** \brief Mask for Ifx_RIF_DBG1_Bits.DD4 */
#define IFX_RIF_DBG1_DD4_MSK (0xffffu)

/** \brief Offset for Ifx_RIF_DBG1_Bits.DD4 */
#define IFX_RIF_DBG1_DD4_OFF (16u)

/** \brief Length for Ifx_RIF_OCS_Bits.TGS */
#define IFX_RIF_OCS_TGS_LEN (2u)

/** \brief Mask for Ifx_RIF_OCS_Bits.TGS */
#define IFX_RIF_OCS_TGS_MSK (0x3u)

/** \brief Offset for Ifx_RIF_OCS_Bits.TGS */
#define IFX_RIF_OCS_TGS_OFF (0u)

/** \brief Length for Ifx_RIF_OCS_Bits.TGB */
#define IFX_RIF_OCS_TGB_LEN (1u)

/** \brief Mask for Ifx_RIF_OCS_Bits.TGB */
#define IFX_RIF_OCS_TGB_MSK (0x1u)

/** \brief Offset for Ifx_RIF_OCS_Bits.TGB */
#define IFX_RIF_OCS_TGB_OFF (2u)

/** \brief Length for Ifx_RIF_OCS_Bits.TG_P */
#define IFX_RIF_OCS_TG_P_LEN (1u)

/** \brief Mask for Ifx_RIF_OCS_Bits.TG_P */
#define IFX_RIF_OCS_TG_P_MSK (0x1u)

/** \brief Offset for Ifx_RIF_OCS_Bits.TG_P */
#define IFX_RIF_OCS_TG_P_OFF (3u)

/** \brief Length for Ifx_RIF_OCS_Bits.SUS */
#define IFX_RIF_OCS_SUS_LEN (4u)

/** \brief Mask for Ifx_RIF_OCS_Bits.SUS */
#define IFX_RIF_OCS_SUS_MSK (0xfu)

/** \brief Offset for Ifx_RIF_OCS_Bits.SUS */
#define IFX_RIF_OCS_SUS_OFF (24u)

/** \brief Length for Ifx_RIF_OCS_Bits.SUS_P */
#define IFX_RIF_OCS_SUS_P_LEN (1u)

/** \brief Mask for Ifx_RIF_OCS_Bits.SUS_P */
#define IFX_RIF_OCS_SUS_P_MSK (0x1u)

/** \brief Offset for Ifx_RIF_OCS_Bits.SUS_P */
#define IFX_RIF_OCS_SUS_P_OFF (28u)

/** \brief Length for Ifx_RIF_OCS_Bits.SUSSTA */
#define IFX_RIF_OCS_SUSSTA_LEN (1u)

/** \brief Mask for Ifx_RIF_OCS_Bits.SUSSTA */
#define IFX_RIF_OCS_SUSSTA_MSK (0x1u)

/** \brief Offset for Ifx_RIF_OCS_Bits.SUSSTA */
#define IFX_RIF_OCS_SUSSTA_OFF (29u)

/** \brief Length for Ifx_RIF_KRSTCLR_Bits.CLR */
#define IFX_RIF_KRSTCLR_CLR_LEN (1u)

/** \brief Mask for Ifx_RIF_KRSTCLR_Bits.CLR */
#define IFX_RIF_KRSTCLR_CLR_MSK (0x1u)

/** \brief Offset for Ifx_RIF_KRSTCLR_Bits.CLR */
#define IFX_RIF_KRSTCLR_CLR_OFF (0u)

/** \brief Length for Ifx_RIF_KRST1_Bits.RST */
#define IFX_RIF_KRST1_RST_LEN (1u)

/** \brief Mask for Ifx_RIF_KRST1_Bits.RST */
#define IFX_RIF_KRST1_RST_MSK (0x1u)

/** \brief Offset for Ifx_RIF_KRST1_Bits.RST */
#define IFX_RIF_KRST1_RST_OFF (0u)

/** \brief Length for Ifx_RIF_KRST0_Bits.RST */
#define IFX_RIF_KRST0_RST_LEN (1u)

/** \brief Mask for Ifx_RIF_KRST0_Bits.RST */
#define IFX_RIF_KRST0_RST_MSK (0x1u)

/** \brief Offset for Ifx_RIF_KRST0_Bits.RST */
#define IFX_RIF_KRST0_RST_OFF (0u)

/** \brief Length for Ifx_RIF_KRST0_Bits.RSTSTAT */
#define IFX_RIF_KRST0_RSTSTAT_LEN (1u)

/** \brief Mask for Ifx_RIF_KRST0_Bits.RSTSTAT */
#define IFX_RIF_KRST0_RSTSTAT_MSK (0x1u)

/** \brief Offset for Ifx_RIF_KRST0_Bits.RSTSTAT */
#define IFX_RIF_KRST0_RSTSTAT_OFF (1u)

/** \brief Length for Ifx_RIF_ACCEN0_Bits.EN0 */
#define IFX_RIF_ACCEN0_EN0_LEN (1u)

/** \brief Mask for Ifx_RIF_ACCEN0_Bits.EN0 */
#define IFX_RIF_ACCEN0_EN0_MSK (0x1u)

/** \brief Offset for Ifx_RIF_ACCEN0_Bits.EN0 */
#define IFX_RIF_ACCEN0_EN0_OFF (0u)

/** \brief Length for Ifx_RIF_ACCEN0_Bits.EN1 */
#define IFX_RIF_ACCEN0_EN1_LEN (1u)

/** \brief Mask for Ifx_RIF_ACCEN0_Bits.EN1 */
#define IFX_RIF_ACCEN0_EN1_MSK (0x1u)

/** \brief Offset for Ifx_RIF_ACCEN0_Bits.EN1 */
#define IFX_RIF_ACCEN0_EN1_OFF (1u)

/** \brief Length for Ifx_RIF_ACCEN0_Bits.EN2 */
#define IFX_RIF_ACCEN0_EN2_LEN (1u)

/** \brief Mask for Ifx_RIF_ACCEN0_Bits.EN2 */
#define IFX_RIF_ACCEN0_EN2_MSK (0x1u)

/** \brief Offset for Ifx_RIF_ACCEN0_Bits.EN2 */
#define IFX_RIF_ACCEN0_EN2_OFF (2u)

/** \brief Length for Ifx_RIF_ACCEN0_Bits.EN3 */
#define IFX_RIF_ACCEN0_EN3_LEN (1u)

/** \brief Mask for Ifx_RIF_ACCEN0_Bits.EN3 */
#define IFX_RIF_ACCEN0_EN3_MSK (0x1u)

/** \brief Offset for Ifx_RIF_ACCEN0_Bits.EN3 */
#define IFX_RIF_ACCEN0_EN3_OFF (3u)

/** \brief Length for Ifx_RIF_ACCEN0_Bits.EN4 */
#define IFX_RIF_ACCEN0_EN4_LEN (1u)

/** \brief Mask for Ifx_RIF_ACCEN0_Bits.EN4 */
#define IFX_RIF_ACCEN0_EN4_MSK (0x1u)

/** \brief Offset for Ifx_RIF_ACCEN0_Bits.EN4 */
#define IFX_RIF_ACCEN0_EN4_OFF (4u)

/** \brief Length for Ifx_RIF_ACCEN0_Bits.EN5 */
#define IFX_RIF_ACCEN0_EN5_LEN (1u)

/** \brief Mask for Ifx_RIF_ACCEN0_Bits.EN5 */
#define IFX_RIF_ACCEN0_EN5_MSK (0x1u)

/** \brief Offset for Ifx_RIF_ACCEN0_Bits.EN5 */
#define IFX_RIF_ACCEN0_EN5_OFF (5u)

/** \brief Length for Ifx_RIF_ACCEN0_Bits.EN6 */
#define IFX_RIF_ACCEN0_EN6_LEN (1u)

/** \brief Mask for Ifx_RIF_ACCEN0_Bits.EN6 */
#define IFX_RIF_ACCEN0_EN6_MSK (0x1u)

/** \brief Offset for Ifx_RIF_ACCEN0_Bits.EN6 */
#define IFX_RIF_ACCEN0_EN6_OFF (6u)

/** \brief Length for Ifx_RIF_ACCEN0_Bits.EN7 */
#define IFX_RIF_ACCEN0_EN7_LEN (1u)

/** \brief Mask for Ifx_RIF_ACCEN0_Bits.EN7 */
#define IFX_RIF_ACCEN0_EN7_MSK (0x1u)

/** \brief Offset for Ifx_RIF_ACCEN0_Bits.EN7 */
#define IFX_RIF_ACCEN0_EN7_OFF (7u)

/** \brief Length for Ifx_RIF_ACCEN0_Bits.EN8 */
#define IFX_RIF_ACCEN0_EN8_LEN (1u)

/** \brief Mask for Ifx_RIF_ACCEN0_Bits.EN8 */
#define IFX_RIF_ACCEN0_EN8_MSK (0x1u)

/** \brief Offset for Ifx_RIF_ACCEN0_Bits.EN8 */
#define IFX_RIF_ACCEN0_EN8_OFF (8u)

/** \brief Length for Ifx_RIF_ACCEN0_Bits.EN9 */
#define IFX_RIF_ACCEN0_EN9_LEN (1u)

/** \brief Mask for Ifx_RIF_ACCEN0_Bits.EN9 */
#define IFX_RIF_ACCEN0_EN9_MSK (0x1u)

/** \brief Offset for Ifx_RIF_ACCEN0_Bits.EN9 */
#define IFX_RIF_ACCEN0_EN9_OFF (9u)

/** \brief Length for Ifx_RIF_ACCEN0_Bits.EN10 */
#define IFX_RIF_ACCEN0_EN10_LEN (1u)

/** \brief Mask for Ifx_RIF_ACCEN0_Bits.EN10 */
#define IFX_RIF_ACCEN0_EN10_MSK (0x1u)

/** \brief Offset for Ifx_RIF_ACCEN0_Bits.EN10 */
#define IFX_RIF_ACCEN0_EN10_OFF (10u)

/** \brief Length for Ifx_RIF_ACCEN0_Bits.EN11 */
#define IFX_RIF_ACCEN0_EN11_LEN (1u)

/** \brief Mask for Ifx_RIF_ACCEN0_Bits.EN11 */
#define IFX_RIF_ACCEN0_EN11_MSK (0x1u)

/** \brief Offset for Ifx_RIF_ACCEN0_Bits.EN11 */
#define IFX_RIF_ACCEN0_EN11_OFF (11u)

/** \brief Length for Ifx_RIF_ACCEN0_Bits.EN12 */
#define IFX_RIF_ACCEN0_EN12_LEN (1u)

/** \brief Mask for Ifx_RIF_ACCEN0_Bits.EN12 */
#define IFX_RIF_ACCEN0_EN12_MSK (0x1u)

/** \brief Offset for Ifx_RIF_ACCEN0_Bits.EN12 */
#define IFX_RIF_ACCEN0_EN12_OFF (12u)

/** \brief Length for Ifx_RIF_ACCEN0_Bits.EN13 */
#define IFX_RIF_ACCEN0_EN13_LEN (1u)

/** \brief Mask for Ifx_RIF_ACCEN0_Bits.EN13 */
#define IFX_RIF_ACCEN0_EN13_MSK (0x1u)

/** \brief Offset for Ifx_RIF_ACCEN0_Bits.EN13 */
#define IFX_RIF_ACCEN0_EN13_OFF (13u)

/** \brief Length for Ifx_RIF_ACCEN0_Bits.EN14 */
#define IFX_RIF_ACCEN0_EN14_LEN (1u)

/** \brief Mask for Ifx_RIF_ACCEN0_Bits.EN14 */
#define IFX_RIF_ACCEN0_EN14_MSK (0x1u)

/** \brief Offset for Ifx_RIF_ACCEN0_Bits.EN14 */
#define IFX_RIF_ACCEN0_EN14_OFF (14u)

/** \brief Length for Ifx_RIF_ACCEN0_Bits.EN15 */
#define IFX_RIF_ACCEN0_EN15_LEN (1u)

/** \brief Mask for Ifx_RIF_ACCEN0_Bits.EN15 */
#define IFX_RIF_ACCEN0_EN15_MSK (0x1u)

/** \brief Offset for Ifx_RIF_ACCEN0_Bits.EN15 */
#define IFX_RIF_ACCEN0_EN15_OFF (15u)

/** \brief Length for Ifx_RIF_ACCEN0_Bits.EN16 */
#define IFX_RIF_ACCEN0_EN16_LEN (1u)

/** \brief Mask for Ifx_RIF_ACCEN0_Bits.EN16 */
#define IFX_RIF_ACCEN0_EN16_MSK (0x1u)

/** \brief Offset for Ifx_RIF_ACCEN0_Bits.EN16 */
#define IFX_RIF_ACCEN0_EN16_OFF (16u)

/** \brief Length for Ifx_RIF_ACCEN0_Bits.EN17 */
#define IFX_RIF_ACCEN0_EN17_LEN (1u)

/** \brief Mask for Ifx_RIF_ACCEN0_Bits.EN17 */
#define IFX_RIF_ACCEN0_EN17_MSK (0x1u)

/** \brief Offset for Ifx_RIF_ACCEN0_Bits.EN17 */
#define IFX_RIF_ACCEN0_EN17_OFF (17u)

/** \brief Length for Ifx_RIF_ACCEN0_Bits.EN18 */
#define IFX_RIF_ACCEN0_EN18_LEN (1u)

/** \brief Mask for Ifx_RIF_ACCEN0_Bits.EN18 */
#define IFX_RIF_ACCEN0_EN18_MSK (0x1u)

/** \brief Offset for Ifx_RIF_ACCEN0_Bits.EN18 */
#define IFX_RIF_ACCEN0_EN18_OFF (18u)

/** \brief Length for Ifx_RIF_ACCEN0_Bits.EN19 */
#define IFX_RIF_ACCEN0_EN19_LEN (1u)

/** \brief Mask for Ifx_RIF_ACCEN0_Bits.EN19 */
#define IFX_RIF_ACCEN0_EN19_MSK (0x1u)

/** \brief Offset for Ifx_RIF_ACCEN0_Bits.EN19 */
#define IFX_RIF_ACCEN0_EN19_OFF (19u)

/** \brief Length for Ifx_RIF_ACCEN0_Bits.EN20 */
#define IFX_RIF_ACCEN0_EN20_LEN (1u)

/** \brief Mask for Ifx_RIF_ACCEN0_Bits.EN20 */
#define IFX_RIF_ACCEN0_EN20_MSK (0x1u)

/** \brief Offset for Ifx_RIF_ACCEN0_Bits.EN20 */
#define IFX_RIF_ACCEN0_EN20_OFF (20u)

/** \brief Length for Ifx_RIF_ACCEN0_Bits.EN21 */
#define IFX_RIF_ACCEN0_EN21_LEN (1u)

/** \brief Mask for Ifx_RIF_ACCEN0_Bits.EN21 */
#define IFX_RIF_ACCEN0_EN21_MSK (0x1u)

/** \brief Offset for Ifx_RIF_ACCEN0_Bits.EN21 */
#define IFX_RIF_ACCEN0_EN21_OFF (21u)

/** \brief Length for Ifx_RIF_ACCEN0_Bits.EN22 */
#define IFX_RIF_ACCEN0_EN22_LEN (1u)

/** \brief Mask for Ifx_RIF_ACCEN0_Bits.EN22 */
#define IFX_RIF_ACCEN0_EN22_MSK (0x1u)

/** \brief Offset for Ifx_RIF_ACCEN0_Bits.EN22 */
#define IFX_RIF_ACCEN0_EN22_OFF (22u)

/** \brief Length for Ifx_RIF_ACCEN0_Bits.EN23 */
#define IFX_RIF_ACCEN0_EN23_LEN (1u)

/** \brief Mask for Ifx_RIF_ACCEN0_Bits.EN23 */
#define IFX_RIF_ACCEN0_EN23_MSK (0x1u)

/** \brief Offset for Ifx_RIF_ACCEN0_Bits.EN23 */
#define IFX_RIF_ACCEN0_EN23_OFF (23u)

/** \brief Length for Ifx_RIF_ACCEN0_Bits.EN24 */
#define IFX_RIF_ACCEN0_EN24_LEN (1u)

/** \brief Mask for Ifx_RIF_ACCEN0_Bits.EN24 */
#define IFX_RIF_ACCEN0_EN24_MSK (0x1u)

/** \brief Offset for Ifx_RIF_ACCEN0_Bits.EN24 */
#define IFX_RIF_ACCEN0_EN24_OFF (24u)

/** \brief Length for Ifx_RIF_ACCEN0_Bits.EN25 */
#define IFX_RIF_ACCEN0_EN25_LEN (1u)

/** \brief Mask for Ifx_RIF_ACCEN0_Bits.EN25 */
#define IFX_RIF_ACCEN0_EN25_MSK (0x1u)

/** \brief Offset for Ifx_RIF_ACCEN0_Bits.EN25 */
#define IFX_RIF_ACCEN0_EN25_OFF (25u)

/** \brief Length for Ifx_RIF_ACCEN0_Bits.EN26 */
#define IFX_RIF_ACCEN0_EN26_LEN (1u)

/** \brief Mask for Ifx_RIF_ACCEN0_Bits.EN26 */
#define IFX_RIF_ACCEN0_EN26_MSK (0x1u)

/** \brief Offset for Ifx_RIF_ACCEN0_Bits.EN26 */
#define IFX_RIF_ACCEN0_EN26_OFF (26u)

/** \brief Length for Ifx_RIF_ACCEN0_Bits.EN27 */
#define IFX_RIF_ACCEN0_EN27_LEN (1u)

/** \brief Mask for Ifx_RIF_ACCEN0_Bits.EN27 */
#define IFX_RIF_ACCEN0_EN27_MSK (0x1u)

/** \brief Offset for Ifx_RIF_ACCEN0_Bits.EN27 */
#define IFX_RIF_ACCEN0_EN27_OFF (27u)

/** \brief Length for Ifx_RIF_ACCEN0_Bits.EN28 */
#define IFX_RIF_ACCEN0_EN28_LEN (1u)

/** \brief Mask for Ifx_RIF_ACCEN0_Bits.EN28 */
#define IFX_RIF_ACCEN0_EN28_MSK (0x1u)

/** \brief Offset for Ifx_RIF_ACCEN0_Bits.EN28 */
#define IFX_RIF_ACCEN0_EN28_OFF (28u)

/** \brief Length for Ifx_RIF_ACCEN0_Bits.EN29 */
#define IFX_RIF_ACCEN0_EN29_LEN (1u)

/** \brief Mask for Ifx_RIF_ACCEN0_Bits.EN29 */
#define IFX_RIF_ACCEN0_EN29_MSK (0x1u)

/** \brief Offset for Ifx_RIF_ACCEN0_Bits.EN29 */
#define IFX_RIF_ACCEN0_EN29_OFF (29u)

/** \brief Length for Ifx_RIF_ACCEN0_Bits.EN30 */
#define IFX_RIF_ACCEN0_EN30_LEN (1u)

/** \brief Mask for Ifx_RIF_ACCEN0_Bits.EN30 */
#define IFX_RIF_ACCEN0_EN30_MSK (0x1u)

/** \brief Offset for Ifx_RIF_ACCEN0_Bits.EN30 */
#define IFX_RIF_ACCEN0_EN30_OFF (30u)

/** \brief Length for Ifx_RIF_ACCEN0_Bits.EN31 */
#define IFX_RIF_ACCEN0_EN31_LEN (1u)

/** \brief Mask for Ifx_RIF_ACCEN0_Bits.EN31 */
#define IFX_RIF_ACCEN0_EN31_MSK (0x1u)

/** \brief Offset for Ifx_RIF_ACCEN0_Bits.EN31 */
#define IFX_RIF_ACCEN0_EN31_OFF (31u)

/** \}  */
/******************************************************************************/
/******************************************************************************/
#endif /* IFXRIF_BF_H */
